 # Theory

The schematic of the amplifier bias is shown in Fig 2(a). We use the same transistor, the BFU550, for the PA and LNA to simplify construction. The difference between the two designs will be the bias condition and the input and output matching network impedances. The gray portion of the bias network is the DC bias. R2 sets the base current for Q1. R1 and C3 form a simple feedback circuit that helps regulate the operating voltage on C3. The input voltage, approximately 9V from a 9V battery, is reduced by the voltage drop in R1. As the collector current increases (DC), this drop will increase, reducing the voltage on the bias resistor R2, causing the bias to reduce and with it a rduction in collector collector current. This feedback network is not critical to the biasing; however, it assists in bias regulation. The RF path is through Q1, to the output load (C1 and C2 are simple DC blocking capacitors). The amplifiers run in Class-A (linear) and Class-AB (non-linear) depending on the input signal. Small signals will be Class-A . Figure 2: (a) Schematic of PA and LNA. R1 is 75k for LNA and 10k for PA. (b) Load pull results showing ideal load impedance. Also shown is the input impedance for that load impedance. (c) Gain and NF circles for LNA. The source impedance is a tradeoff between noise and gain. The load impedance is set for maximum gain. (d) & (e) Simulation vs. measured results for the LNA and PA.

The LNA is biased at 3 mA, which is closer to the lower noise operation of the transistor as shown in the datasheet. The amplifier is then simulated to find the output impedance that achieves the maximum gain (Gmax). This was found, Fig. 2(c), to be 60+100j . Note that the maximum gain circles (blue) extend off of the Smith Chart. We chose a point on the highest circle, but closest to the origin, i.e. closest to 50 , in order to minimize the impedance transformation needed. The source network is where the LNA differs from a simple ac amplifier. The input referred noise of the amplifier is dependent on the impedance seen at the input. As a result, an impedance matched input may not provide the lowest noise operation. Many transistors have been measured and modeled for the source impedance that yields the lowest noise – measured by the noise figure (NF). The noise factor, F, is the ratio of the signal to noise ratio of the input to the signal to noise ratio of the output, NF is 10log10F. Noise figure (NF) is always greater than zero. Figure 2(c) shows the gain circles for input impedance that achieves maximum gain (green), it assumes the load is the load that achieves maximum gain, i.e. 60+100j. Plotted in brown are the source impedances for minimum NF. Note the two overlap but are not identical. We selected a source impedance of 11+10j as a compromise between high-gain and minimal noise.

For all impedance matching networks, a simple two transmission line (t-line) network was chosen, which consists of a series t-line with an open t-line stub, Fig. 2(a). While one can calculate the lengths of each t-line [L1 through L4 Fig. 2(a)], most commercial simulation tools can “tune” component parameters. The characteristic impedance of the t-lines was fixed at 50 for ease of fabrication; only the lengths were modified. Our Radar was designed in National Instruments AWR Microwave Office, which allowed us to tune the lengths on a slider. In less than a minute one can adjust the lengths by trial and error to get the desired impedances. An optimization feature in the software can also find suitable values. The network is then attached to a 50 t-line to extend the network to the edge of the board in order to connect a PCB mount SMA connector.

Figure 2(c) show the S-parameter results of the PA and LNA. The general performance is good, however there are discrepancies from simulations. These discrepancies result from the impedance matching networks not being accurate due to a lack of consideration of the board edges and variations in fabrication using a simple 2-D foil cutter.

# Design

Use the Biased for LNA in your template file as a starting design.

The design of the low noise amplifier is explained in the following videos. The basic steps for design are as follows:

1. Bias your transistor (already done in template) and measure the S-parameters.
2. Plot the gain circles for input and output impedance to find the source and load impedances for maximum gain.
3. Plot the noise figure circles for minimum noise.
4. Examine the tradeoff between noise and gain in the source impedance, and set a source impedance.
6. Assemble the amplifier with biased transistor core and source/load impedance matching networks.
7. Perform final EM analysis (optional).

## Part 0 – BJT Biasing (this may be skipped as the BJT is already biased in the template).

Web version of video with step-by-step images and transcript here.

## Part 1 – Determine source/load impedance for noise and gain.

Web version of video with step-by-step images and transcript here.

# Synthesizing Impedances

To synthesize the impedances, we will take a short-cut and assume a topology for our impedance synthesizer and simply “tune” it to give us the impedances we need. Below is a picture of the two impedance synthesis networks. The one on the left impedance transforms 50 Ohms to the target impedance for the input of the PA (the complex conjugate of the PA input impedance, ZS=R1+X1j). The one on the right impedance transforms the 50 Ohm load to the target impedance of the PA output (this is the value found during Load-Pull, ZL=R2+X2j). We will demonstrate how to design the right imepdance matching network for ZL. The same procedure can be used for the left, or input matching load.

There are three transmssion lines of lengths: L1, L2 and L3. All are 50 Ohm transmission lines (2.85 mm width using our PCB). L3 is a 10 mm long transmision line used to connect to the 50 Ohm SMA connector. Its length does not change. L1 connects to the PA output and the junction of the three transmission lines. It will be adjustable in length. L2 intersects between L1 and L3 and is open at the other end. It is an open “stub.”

The impedance transformation is done by varying L1 and L2, such that the impedance looking into L1 at the left equals the target ZL.

Create the following schematic for the impedance transformation network. For convenience name it OutputMatch. You should create a second schematic named InputMatch. Both have the same schematic, but different values of L1 and L2. MLIN can be created using Ctrl-L then typing MLIN to find component. MTEEX\$ is a “T” junction that will automatically size to connect to line widths at its ports 1,2 and 3. Since these lines are all 50 Ohm, the widths are the same. MLEFX is a transmission line that is open at one end. The EM model properly models the open end. If we simply used MLIN and didn’t connect one end, the EM model would not properly model it.

Use Ctrl+E and click anywhere above the circuit and an equation will appear. Type L1=20 and L2=20. Then enter the lengths of the left and bottom (open stup) transmission lines as L1 and L2. The units are determined by the component (mm). Now, on each equation Right Click -> Properties and then click tune and enter step size as 1 as shown below. The equations will turn blue in the schematic to show they are now tunable. Projects -> Add New Graph, label “Output Impedance Transformation” and select Smith Chart. Right Click -> New Measurement and add S11 and S22 as complex impedances as shown below. Make sure Data Source Name is set to your schematic name. In this example, we named our schematic “Simple Zsynth.” If you haven’t set frequencies, go to Options->Project Options and set the frequencies below (make sure to select and click Replace). Now run the simulation by clicking on the lightening bolt icon found on the icon toolbar at the top of the window. It will be under the Tools and Scripts text menu labels. Your simulation should look like this. Note we have clicked the tune icon (upper right on icon tool bar) and a tuner window as shown up on the left. We have also added a marker (Right Click -> Add Marker) to show 950 MHz. Double click the marker text box to ensure you have the complex impedance shown and Denormalized to 50 Ohms. It is very important to know which impedance you are tuning. In the example, we are tuning S22 not S11 as Port 1 is connected to 50 Ohms and is not being adjusted. We are impedance transforming the 50 Ohms at Port 1 to the desired impedance. For example purposes, lets transform to ZL=100+50j.

Adjust L1 and L2 by sliding the tuner bars. You can extend the tuning range from 40 (set as default) to a higher value by changing the Max value under L1 and L2. You will clickly gain intuition on how the marker moves. After about 30 sec, we have achieved the following: Which is close to our target impedance. We could modify the step size to below 1 mm to achieve more precision or simply use this as our impedance. It will be difficult to match exactly your target impedance with this network if you are far away from 50 Ohms as your target impedance.

You can now go to your schematic, View-> Layout and see the layout below. I have used Ctrl-A to select all then Edit->Snap Together to do an auto layout. Note that the 10mm feed line is on the left in this layout, but for our PA, it would be on the right as that is the output.

You can repeat the design process for the input matching network.

## Part 3 – Complete amplifier, layout and EM simulations

The LNA is completed exactly as the PA was. Please follow the same steps. The only difference is the choice of impedance matching networks on the input/output.

Do NOT meander the impedance matching stages. The design kit has an easy-to-build format that does not require meandering (curving the lines to fit on a board).